The invention relates to the field of microcontrollers, and in particular to the field of direct memory access (DMA) devices.
DMA modules are employed in microcomputer controller systems and microcontroller systems to relieve the CPU from routinely recurring data transfer tasks. A DMA module may be viewed as a kind of specialized processor which receives a specification for a memory area which must be accessed, for example, a start address and stop address, or a start address and a number of subsequent memory locations, and which outputs the addresses of a specified range in rapid succession to an address bus to enable rapid reading from or writing to the memory area. A DMA module thus enables the rapid transfer of data between memory areas, or between one memory area and a peripheral device, without taking up any of the processing power of the CPU. A DMA module thus relieves the CPU from simple data transfer tasks, thereby increasing the average achievable performance of the CPU.
If the CPU and the DMA module share a common bus for access to the memory, then for every bus cycle in which the DMA module accesses the memory for a read or write operation the CPU must be halted to prevent the CPU from attempting to initiate access at the same time. Although during this procedure, known as “cycle stealing,” the operation of the CPU is slightly diminished, the number of CPU cycles lost is significantly less than if the CPU itself had to control the data transfer. Hence, use of the DMA module enhances the performance of the CPU.
A DMA module always proceeds from a start address to a stop address. In the conventional approach, the two addresses are stored in internal registers of the DMA module. As a result, it is possible with a single bus cycle to output an address, to read or write a memory location identified by the address, and to advance an address counter for the following read or write operation.
A DMA module with two registers of this type is able to perform only one DMA process at a time. If a running DMA process has to be interrupted to perform a DMA process of higher priority, the register contents of the currently running, lower priority process with its current values from the DMA module must be swapped out and temporarily stored to allow the relevant parameters of the higher priority process to be loaded and executed. This swapping out and loading of addresses slows down the DMA module, and the microcontroller along with it, and is therefore not desirable.
A conceivable approach would be to equip a DMA module of this type with a plurality of register pairs that would hold the parameters of the different DMA processes. As a result, to interrupt a currently running DMA process in favor of a higher-priority process the system would switch to a different register pair.
The problem with this approach, however, is that registers of this type have a relatively large space requirement on a semiconductor substrate, this requirement typically being five times the requirement of a memory element of identical size within RAM. This large space requirement makes fabrication of multi-process DMA modules expensive.
Therefore, there is a need for a DMA module which has a relatively small space requirement, and a method of operating a DMA module in which such small-area DMA modules may be employed.